A Capacitor DAC for Charge Redistribution Analog to Digital Converter with Successive Approximation

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F18%3A00331446" target="_blank" >RIV/68407700:21230/18:00331446 - isvavai.cz</a>
Alternative codes found
RIV/68407700:21340/18:00331446
Result on the web
<a href="https://pos.sissa.it/343/094/" target="_blank" >https://pos.sissa.it/343/094/</a>
DOI - Digital Object Identifier
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Result language
angličtina
Original language name
A Capacitor DAC for Charge Redistribution Analog to Digital Converter with Successive Approximation
Original language description
The recent analog to digital converters, with the successive approximation (SAR ADC), are widely used for their high speed, low power operation, and accuracy. SAR ADC demands precise internal digital to analog converter (DAC). To save power, the DAC is mainly implemented using capacitors (CDAC). Its precision depends mostly on layout implementation which must minimize the various parasitic effects. This paper presents two new layout design approaches of CDAC for SAR ADC used in a pixel detector implemented in 180 nm SOI technology.
Czech name
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Czech description
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Project
<a href="/en/project/EF16_019%2F0000778" target="_blank" >EF16_019/0000778: Center for advanced applied science</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
A Capacitor DAC for Charge Redistribution Analog to Digital Converter with Successive Approximation
ISBN
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ISSN
1824-8039
e-ISSN
1824-8039
Number of pages
5
Pages from-to
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Publisher name
Proceedigns of Science
Place of publication
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Event location
Antwerpy
Event date
Sep 17, 2018
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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