High Performance IIR Filter FPGA Implementation Utilizing SOS Microcode Core

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F19%3A00335986" target="_blank" >RIV/68407700:21230/19:00335986 - isvavai.cz</a>

Alternative codes found

RIV/68407700:21260/19:00335986

Result on the web

<a href="https://doi.org/10.14311/TEE.2019.2.022" target="_blank" >https://doi.org/10.14311/TEE.2019.2.022</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.14311/TEE.2019.2.022" target="_blank" >10.14311/TEE.2019.2.022</a>

Result language

angličtina

Original language name

High Performance IIR Filter FPGA Implementation Utilizing SOS Microcode Core

Original language description

This paper discusses the methods of optimal IIR filter FPGA implementation. The methods are focused on the reduction of occupied resources and increasing data throughput. Higher demands on an internal controller complexity are successfully solved by utilizing programmable microcode controller. The novelty of SOS core and its capabilities are presented and different variants of SOS core are assessed. The workflow of IIR filter design using MATLAB considering rounded coefficient method is demonstrated.

Czech name

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Czech description

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Type

J_ost - Miscellaneous article in a specialist periodical

CEP classification

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OECD FORD branch

20205 - Automation and control systems

Project

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Continuities

N - Vyzkumna aktivita podporovana z neverejnych zdroju

Publication year

2019

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

Transaction on Electrical Engineering

ISSN

1805-3386

e-ISSN

1805-3386

Volume of the periodical

8

Issue of the periodical within the volume

2

Country of publishing house

CZ - CZECH REPUBLIC

Number of pages

4

Pages from-to

22-25

UT code for WoS article

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EID of the result in the Scopus database

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