Spatial Systematic Mismatch Assessment of Pre-arranged Layout Topologies
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F20%3A00341039" target="_blank" >RIV/68407700:21230/20:00341039 - isvavai.cz</a>
Alternative codes found
RIV/68407700:21340/20:00341039
Result on the web
<a href="https://doi.org/10.1016/j.sse.2020.107822" target="_blank" >https://doi.org/10.1016/j.sse.2020.107822</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1016/j.sse.2020.107822" target="_blank" >10.1016/j.sse.2020.107822</a>
Alternative languages
Result language
angličtina
Original language name
Spatial Systematic Mismatch Assessment of Pre-arranged Layout Topologies
Original language description
A spatial systematic mismatch, occurring in the integrated circuit manufacturing process, leads to differences in parameters for two or more identical devices. It is widely accepted that placing devices into symmetrical patterns reduces the spatial systematic mismatch between their parameters. In this paper, a novel method based on linear and nonlinear parameter gradient modeling for the assessment of pre-arranged matched structures has been proposed. The direction of a parameter gradient against a layout topology on a wafer is unknown. The pre-arranged layout pattern is rotated against the modeled parameter gradient. In each step of the rotation, for example, with a 1-degree resolution, the mismatch between parameters is calculated. The peak mismatch value is then used for the comparison of the different pre-arranged patterns. The proposed method is independent of technology.
Czech name
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Czech description
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Classification
Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
20201 - Electrical and electronic engineering
Result continuities
Project
<a href="/en/project/EF16_019%2F0000778" target="_blank" >EF16_019/0000778: Center for advanced applied science</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2020
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Name of the periodical
Solid-State Electronics
ISSN
0038-1101
e-ISSN
1879-2405
Volume of the periodical
170C
Issue of the periodical within the volume
August
Country of publishing house
NL - THE KINGDOM OF THE NETHERLANDS
Number of pages
8
Pages from-to
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UT code for WoS article
000538178800006
EID of the result in the Scopus database
2-s2.0-85084493088