QtRvSim–RISC-V CPU Simulator for Education with Cache and Pipeline Visualization
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F22%3A00363295" target="_blank" >RIV/68407700:21230/22:00363295 - isvavai.cz</a>
Alternative codes found
RIV/68407700:21240/22:00363295
Result on the web
<a href="https://comparch.edu.cvut.cz/" target="_blank" >https://comparch.edu.cvut.cz/</a>
DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
QtRvSim–RISC-V CPU Simulator for Education with Cache and Pipeline Visualization
Original language description
QtRvSim is RISC-V based computer system simulator designed for teaching and learning computer systems principles. The simulator allows students to run assembly programs and observe the instruction execution on single-cycle and pipelined microarchitectures. The simulator graphically displays the major components in the datapath, including the register file, the arithmetic-logic unit, memory caches, peripherals, and the control unit with control signals. QtRVSim is free and open-source software available on GitHub and as a WebAssembly application online which can be run directly from CTU pages build in cooperation by FEE and FIT faculties. They include even additional course links and materials, see https://comparch.edu.cvut.cz/ .
Czech name
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Czech description
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Classification
Type
R - Software
CEP classification
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OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
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Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace
Others
Publication year
2022
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Internal product ID
QtRvSim
Technical parameters
The project is developed and available according to GNU General Public License (GPL v3). Announced by article Dupák, J.; Píša, P.; Štepanovský, M.; Kočí, K. QtRVSim – RISC-V Simulator for Computer Architectures Classes In: embedded world Conference 2022. Haar: WEKA FACHMEDIEN GmbH, 2022. p. 775-778. ISBN 978-3-645-50194-1. Presented on RISC-V International Academic and Training SIG meeting: QtRvSim - RISC-V Simulator with Cache and Pipeline Visualization https://youtu.be/J6AcPZZ_ISg?t=12 Project referenced by RISC-V International https://riscv.org/exchange/?_sf_s=QtRvSim&_sft_exchange_category=software Used in education at FEE and FIT CTU and three other abroad respected universities.
Economical parameters
Effort/cost estimates by OpenHub https://www.openhub.net/p/qtrvsim/estimated_cost Codebase Size 33,574 lines Estimated Effort 8 person-years Estimated Cost 432 179 USD, about 9,5 mil Kč
Owner IČO
68407700
Owner name
České vysoké učení technické v Praze