Automatic Placer for Analog Circuits Using Integer Linear Programming Warm Started by Graph Drawing

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F23%3A00364869" target="_blank" >RIV/68407700:21230/23:00364869 - isvavai.cz</a>

Alternative codes found

RIV/68407700:21730/23:00364869

Result on the web

<a href="https://doi.org/10.5220/0011789300003396" target="_blank" >https://doi.org/10.5220/0011789300003396</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.5220/0011789300003396" target="_blank" >10.5220/0011789300003396</a>

Result language

angličtina

Original language name

Automatic Placer for Analog Circuits Using Integer Linear Programming Warm Started by Graph Drawing

Original language description

Due to its diversity, the physical design of the Analog and Mixed-Signal Integrated Circuits is not as automated as the physical design of digital Integrated Circuits. The placement process is one of the critical steps of the physical design, and automating it would significantly shorten the design time. We formulate the placement process using an Integer Linear Programming approach, with features to support a specific semiconductor technology. We include an enumeration of possible variants of the circuit’s topological structures, which are afterward considered during optimization. We use the Gurobi solver to minimize both the approximate wire length and the placement area. The results were evaluated by layout design experts and compared with manual designs. We also utilize a graph drawing-based method to generate an initial feasible solution to warm start the Integer Linear Programming solver, which noticeably improves the performance and shortens the computation time (5x to 15x), a nd makes the approach applicable even for larger problem instances containing 100 independent elements. Experiments performed on real-life industrial problem instances show that our graph drawing-enhanced approach can produce high-quality placement in a much shorter time than the designers need.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

—

Continuities

S - Specificky vyzkum na vysokych skolach

Publication year

2023

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Proceedings of the 12th International Conference on Operations Research and Enterprise Systems

ISBN

978-989-758-627-9

ISSN

2184-4372

e-ISSN

2184-4372

Number of pages

11

Pages from-to

106-116

Publisher name

Science and Technology Publications, Lda

Place of publication

Setúbal

Event location

Lisabon

Event date

Feb 19, 2023

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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