Low Latency Digital Radar Target Simulator Design

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F24%3A00375927" target="_blank" >RIV/68407700:21230/24:00375927 - isvavai.cz</a>
Result on the web
<a href="https://doi.org/10.1109/MetroAutomotive61329.2024.10615445" target="_blank" >https://doi.org/10.1109/MetroAutomotive61329.2024.10615445</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/MetroAutomotive61329.2024.10615445" target="_blank" >10.1109/MetroAutomotive61329.2024.10615445</a>

Result language
angličtina
Original language name
Low Latency Digital Radar Target Simulator Design
Original language description
During the digital simulation of the synthetic target to the automotive radar sensor, low latency is an important parameter. This parameter defines the minimum range of the simulated obstacle. Each 6.67 ns of latency increases the minimum target distance per meter. The primary source of latency is the conversion of the radar signal between the analog and digital domains. This paper thoroughly analyzes delay sources in digital radar simulation. On the basis of this analysis, the low latency simulator design is presented. The design was evaluated with an FPGA based target simulator. The experimental results present the overall system latency and comparison with similar solutions.
Czech name
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Czech description
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Project
—
Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Publication year
2024
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
2024 IEEE International Workshop on Metrology for Automotive
ISBN
979-8-3503-8498-7
ISSN
—
e-ISSN
—
Number of pages
5
Pages from-to
24-28
Publisher name
IEEE
Place of publication
Halifax
Event location
Bologna
Event date
Jun 26, 2024
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
001294453100004

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