SHIFT-ADD Neural Architecture
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F99%3A03018897" target="_blank" >RIV/68407700:21230/99:03018897 - isvavai.cz</a>
Result on the web
—
DOI - Digital Object Identifier
—
Alternative languages
Result language
angličtina
Original language name
SHIFT-ADD Neural Architecture
Original language description
This article is focused on implementation of artifical neural networks in hardware. The article presents an overview of the shift-add arithmetics based on the linearly approximated 2^x and log2x functions, implementation of the perceptron and RBF processing unit,and on-chip implementation.
Czech name
—
Czech description
—
Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
—
Result continuities
Project
—
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)
Others
Publication year
1999
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of ICECS'99
ISBN
0-7803-5682-9
ISSN
—
e-ISSN
—
Number of pages
4
Pages from-to
—
Publisher name
IEEE
Place of publication
Piscataway, NJ
Event location
—
Event date
—
Type of event by nationality
—
UT code for WoS article
—