Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F10%3A00169351" target="_blank" >RIV/68407700:21240/10:00169351 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG
Original language description
In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method is targeted to systems on chip (SoCs) provided with the P1500 test standard. The RESPIN architecture can be used for test patterns decompression. The main idea is based on finding the best overlap of test patterns during the test generation, unlike other methods, which are based on efficient overlapping of pre-generated test patterns. The proposed algorithm takes advantage of an implicit test representation as SAT problem instances. The results of test patterns compression obtained for standard ISCAS'85 and '89 benchmark circuits are shown and compared with competitive test compression methods.
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: SoC circuits reliability and availability improvement</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 13th Euromicro Conference on Digital System Design
ISBN
978-0-7695-4171-6
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
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Publisher name
IEEE Computer Society Press
Place of publication
Los Alamitos
Event location
Lille
Event date
Sep 1, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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