A Novel and Efficient Method to Initialize FPGA Embedded Memory Content in Asymptotically Constant Time

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F16%3A00303813" target="_blank" >RIV/68407700:21240/16:00303813 - isvavai.cz</a>
Result on the web
<a href="http://ieeexplore.ieee.org/document/7857146/" target="_blank" >http://ieeexplore.ieee.org/document/7857146/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ReConFig.2016.7857146" target="_blank" >10.1109/ReConFig.2016.7857146</a>

Result language
angličtina
Original language name
A Novel and Efficient Method to Initialize FPGA Embedded Memory Content in Asymptotically Constant Time
Original language description
This paper describes analysis and implementation of a new method for maintaining valid content of FPGA memory blocks with an asymptotically constant time synchronous clear ability, that can be useful for (re)initialization to one default value. A particular application can be for high-speed real-time LZ77 lossless compression algorithms, where a dictionary has to be (re)initialized before each run of the implemented compression algorithm. The method is based on two most widely used techniques for clearing the memory content: a linear passage of the memory and clearing each cell by writing a default value and creating a register field providing an (in)valid bit for each memory cell. Our solution combines these two techniques together with the use of FPGA distributed memory blocks implemented in LUTs (Look-Up Tables) to overcome negative features of each previous method without losing the most of positive features. Our solution provides a balance between the two previous techniques and exceeds them in speed, resources utilization and latency of (re)initialization.
Czech name
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Czech description
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Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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