Improved ring oscillator PUF on FPGA and its properties

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F16%3A00304711" target="_blank" >RIV/68407700:21240/16:00304711 - isvavai.cz</a>

Result on the web

<a href="http://dx.doi.org/10.1016/j.micpro.2016.02.005" target="_blank" >http://dx.doi.org/10.1016/j.micpro.2016.02.005</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.micpro.2016.02.005" target="_blank" >10.1016/j.micpro.2016.02.005</a>

Result language

angličtina

Original language name

Improved ring oscillator PUF on FPGA and its properties

Original language description

PUFs (Physical Unclonable Function) are increasingly used in proposals of security architectures for device identification and cryptographic key generation. Many PUF designs for FPGAs proposed up to this day are based on ring oscillators (RO). The classical approach is to compare frequencies of ROs and produce a single output bit from each pair of ROs based on the result of comparison of their frequencies. This ROPUF design requires all ROs to be mutually symmetric and also the number of pairs of ROs is limited in order to preserve the independence of bits in the PUF response. This led us to design a new ROPUF on FPGA which is capable of generating multiple output bits from each pair of ROs and is also allowing to create higher number of pairs of ROs, thereby making the use of ROs more efficient than the classical approach. Our PUF design is based on selecting a particular part of a counter value and using it for the PUF output. By applying Gray code on the counter values, we have considerably improved the PUF's statistical properties. In principle, this PUF design does not need the ROs to be mutually symmetric, however, it is shown that this ROPUF design has significantly better properties with varying supply voltage when symmetric ROs are used. All of the presented measurements were performed on Digilent Basys 2 FPGA Boards (Xilinx Spartan3E-100 CP132). In this work, we provide a more detailed description of the PUF design on FPGA and the behaviour of ROs with varying supply voltage. Our proposed PUF architecture offers more output bits with required statistical properties from each RO pair than the classical approach, where frequencies of ROs are compared. The presented improvements significantly reduce the dependence on fluctuation of supply voltage.

Czech name

—

Czech description

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Type

J_x - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)

CEP classification

IN - Informatics

OECD FORD branch

—

Project

<a href="/en/project/GA16-05179S" target="_blank" >GA16-05179S: Fault-Tolerant and Attack-Resistant Architectures Based on Programmable Devices: Research of Interplay and Common Features</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2016

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

Microprocessors and Microsystems

ISSN

0141-9331

e-ISSN

—

Volume of the periodical

47

Issue of the periodical within the volume

November

Country of publishing house

NL - THE KINGDOM OF THE NETHERLANDS

Number of pages

9

Pages from-to

55-63

UT code for WoS article

000390510400007

EID of the result in the Scopus database

2-s2.0-84960976398