Are XORs in logic synthesis really necessary?

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F17%3A00311674" target="_blank" >RIV/68407700:21240/17:00311674 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/DDECS.2017.7934583" target="_blank" >http://dx.doi.org/10.1109/DDECS.2017.7934583</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS.2017.7934583" target="_blank" >10.1109/DDECS.2017.7934583</a>

Result language
angličtina
Original language name
Are XORs in logic synthesis really necessary?
Original language description
This paper follows recent research on insufficient synthesis performance for XOR-intensive circuits, and introduces a novel logic representation with a native support of XOR gates, the XOR-AND-Inverter Graphs (XAIGs). A rewriting algorithm over XAIG has been implemented in the logic synthesis and optimization package ABC, as the first step towards a complete synthesis process. The results show that XAIG based rewriting can help to discover XORs and improves the area of a mapped network in some cases.
Czech name
—
Czech description
—

Project
<a href="/en/project/GA16-05179S" target="_blank" >GA16-05179S: Fault-Tolerant and Attack-Resistant Architectures Based on Programmable Devices: Research of Interplay and Common Features</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems
ISBN
978-1-5386-0472-4
ISSN
—
e-ISSN
2473-2117
Number of pages
6
Pages from-to
134-139
Publisher name
IEEE
Place of publication
Piscataway, NJ
Event location
Dresden
Event date
Apr 19, 2017
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000403405200025

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