A Comparison of Logic Extraction Methods in Hardware-Translated Neural Networks
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F24%3A00375937" target="_blank" >RIV/68407700:21240/24:00375937 - isvavai.cz</a>
Result on the web
<a href="https://doi.org/10.1109/DDECS60919.2024.10508902" target="_blank" >https://doi.org/10.1109/DDECS60919.2024.10508902</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS60919.2024.10508902" target="_blank" >10.1109/DDECS60919.2024.10508902</a>
Alternative languages
Result language
angličtina
Original language name
A Comparison of Logic Extraction Methods in Hardware-Translated Neural Networks
Original language description
Small quantized neural networks with strong requirements on throughput and latency can be translated into combinational logic circuits and synthesized by logic design tools. To capture the function of the network (or a part of it) as a logic function, two approaches have been taken. The first one observes the inputs and outputs, while the network predicts a training set, and uses them directly as specification. The response to activation values that have not occurred in the training set remain unspecified. The other approach uses a complete set of activation values at the input of the examined part. Our study aims to quantify the inaccuracy of the first method, the influence of logic minimization used on accuracy, and the impact on the final synthesized circuit. We also document the quantitative changes in quantized networks.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
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Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace
Others
Publication year
2024
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 27th International Symposium on Design and Diagnostics of Electronic Circuits & Systems
ISBN
979-8-3503-5934-3
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
86-91
Publisher name
IEEE
Place of publication
Piscataway
Event location
Kielce
Event date
Apr 3, 2024
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
001227439800003