PARTIAL DYNAMIC RECONFIGURATION: A TECHNIQUE FOR HIGH RELIABILITY AND SAFETY-CRITICAL FPGA APPLICATIONS
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21260%2F14%3A00226567" target="_blank" >RIV/68407700:21260/14:00226567 - isvavai.cz</a>
Result on the web
<a href="http://www.vedeckekonference.cz/library/proceedings/mmk_2014.pdf" target="_blank" >http://www.vedeckekonference.cz/library/proceedings/mmk_2014.pdf</a>
DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
PARTIAL DYNAMIC RECONFIGURATION: A TECHNIQUE FOR HIGH RELIABILITY AND SAFETY-CRITICAL FPGA APPLICATIONS
Original language description
This paper deals with a new approach to designing high reliability and safety critical applications using Field Programmable Gate Arrays FPGAs). The presented concept is based on partial dynamic reconfiguration, the feature with prospect of making designs smaller in terms of chip area, easily verifiable and testable. Furthermore, the Safety Core principle is introduced.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
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Continuities
N - Vyzkumna aktivita podporovana z neverejnych zdroju
Others
Publication year
2014
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Mezinárodní Masarykova konference pro doktorandy a mladé vědecké pracovníky 2014
ISBN
978-80-87952-07-8
ISSN
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e-ISSN
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Number of pages
7
Pages from-to
3369-3375
Publisher name
MAGNANIMITAS
Place of publication
Hradec Králové
Event location
Hradec Králové
Event date
Dec 15, 2014
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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