Low noise programmable PLL for precise timing systems

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21340%2F12%3A00204166" target="_blank" >RIV/68407700:21340/12:00204166 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Low noise programmable PLL for precise timing systems
Original language description
Low noise programmable phase-locked loop (PLL) is suitable for timing applications serving as system clock. With long term stable reference such as GNSS disciplined oscillator, the PLL provides both long and short term stable frequency. The device accepts 5MHz or 10MHz sine waves typical for long term stable references. Output frequency can be programmed within the interval of 100MHz to 350MHz, which is convenient source clock frequency for high precision timing systems. Programmable output gain and frequency is set via either an UART interface with TTL levels or USB CDC emulating standard serial port. Output signal peak-to-peak amplitude can be set to values of 350mV to 1V into 50 ohms. Phase stability with respect to temperature changes is in the interval of 60°C to 70°C below +-1ps/K.
Czech name
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Czech description
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Project
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Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Publication year
2012
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Internal product ID
14112-12-zavesprg-Mich
Numerical identification
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Technical parameters
intput 5 or 10MHz; output progr. 100-350 MHz / 350-1000 mV; temp. stab. below 1ps/K 60-70 °C; table-top size
Economical parameters
50000,- Kč
Application category by cost
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Owner IČO
68407700
Owner name
ČVUT FJFI
Owner country
CZ - CZECH REPUBLIC
Usage type
N - Využití výsledku jiným subjektem je možné bez nabytí licence (výsledek není licencován)
Licence fee requirement
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Web page
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