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Tools for split RTL circuit into Testable blocks
Developed tools make possible to split circuit written in formal model that was developed on DSC into Testable blocks and design scan chain. Outputs of tools are individual Testable blocks written in verilog....
JC - Počítačový hardware a software
- 2007 •
- X
Rok uplatnění
X - Nezařazeno
RTL Testability Analysis Based on Genetic Algorithm Implementation
The paper deals with a new approach to the RTL testability analysis. The approach is based on genetic algorithms theory and applies registers selected into UUA (Unit Under Analysis) scan chain as a population in ge...
JC - Počítačový hardware a software
- 2001 •
- D
Rok uplatnění
D - Stať ve sborníku
Testability analysis and improvements of a RTL digital circuit
The paper deals with topics, problems and terms which are close to my PhD research and uses them to demonstrate the motivation and goals of my PhD research and thesis. The research is directed to design an efficient RTL testability ...
JC - Počítačový hardware a software
- 2003 •
- D
Rok uplatnění
D - Stať ve sborníku
Formal and Analytical Approaches to the Testability Analysis - the Comparison
The paper deals with two approaches to the RTL testability analysis - formal and analytical ones and their results. The formal approach is based on the theory of set. The reasons for RTL testability an...
JC - Počítačový hardware a software
- 2001 •
- D
Rok uplatnění
D - Stať ve sborníku
RTL Testability Analysis Based on Genetic Algorithm Implementation
The paper deals with a new approach to the RTL testability analysis structure. On the testability analysis basis, UUA modificatins leading to UUA nodes (Unit Under Analysis) scan chain as a popula...
JC - Počítačový hardware a software
- 2001 •
- D
Rok uplatnění
D - Stať ve sborníku
Set of tools for RTL circuits testability analysis
Developed tools can be used for automatic transformation of digital circuit design written in structural VHDL to formal model that was developed on DCS. It is possible to use them for transparent data paths (I-paths) search, testability ...
JC - Počítačový hardware a software
- 2007 •
- X
Rok uplatnění
X - Nezařazeno
Formal Approach to the RTL Testability Analysis
NOT available...
JC - Počítačový hardware a software
- 2000 •
- D
Rok uplatnění
D - Stať ve sborníku
Analytic Approach to RTL Testability Analysis
The paper deals with analytical approach to the RTL testability analysis and its results. Approach is based as on circuit i path analysis, finding i paths, as on difficult to control/observe nodes location. On thes...
JC - Počítačový hardware a software
- 2001 •
- D
Rok uplatnění
D - Stať ve sborníku
Testability Estimation Based on Controllability and Observability Parameters
In the paper a method for estimation the circuit testability on the Register Transfer Level (RTL) is presented. The method allows to perform fast testability and observability measurement for estimation of overall circuit <...
JC - Počítačový hardware a software
- 2006 •
- D
Rok uplatnění
D - Stať ve sborníku
On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits
synthesis run, testability analysis is typically performed only after final logic synthesis. As a consequence, results of the analysis could be obtained when it is very in several ways. In the contribution, it is supposed ...
JC - Počítačový hardware a software
- 2011 •
- D
Rok uplatnění
D - Stať ve sborníku
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