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Dynamically Reconfigurable Process by Multiagent

Dynamically reconfigurable processor with agent is in the core dynamically reconfigurable processor consist of commoncore CPU and dynamically reconfigurable unit (RPU) which is core of dynamic...

BC - Teorie a systémy řízení

  • 2007
  • D
Result

Dynamic Reconfiguration in FPGA-Based SoC Designs

This paper discusses architectural issues arising from the use of dynamic reconfiguration and shows a possible use of dynamic reconfiguration to extend and accelerate a computation performed in system-on-a-chip des...

JC - Počítačový hardware a software

  • 2005
  • D
Result

Dynamic Reconfiguration of FPGAs: a Case Study

FPGA as reconfigurable VLSI devices - methods...

JC - Počítačový hardware a software

  • 2003
  • D
Result

Dynamic Reconfiguration in FPGA-based Designs

This paper discusses architectural issues arising from the use of dynamic reconfiguration and shows a possible use of dynamic reconfiguration to extend and accelerate a computation performed in system-on-a-chip des...

JC - Počítačový hardware a software

  • 2005
  • D
Result

Dynamic Programmable Logic Reconfiguration for Zynq

). This demo shows how the PL can be fully reconfigured without using partial dynamic reconfiguration. This way, at the cost of the longer time needed for reconfiguration of PL we can cover 90% typical applications...

IN - Informatika

  • 2015
  • Gfunk
Result

Partial Dynamic Reconfiguration in Xilinx FPGA Circuits

This application note describes the use of the partial dynamic reconfiguration in Xilinx FPGA circuits. The FIR filter is implemented in Xilinx ML402 evaluation platform....

JC - Počítačový hardware a software

  • 2007
  • A
Result

GPDRC: Generic partial dynamic reconfiguration controller

Implementation of GPDRC (Generic partial dynamic reconfiguration controller) in VHDL. Optimized for XILINX FPGAs.

JC - Počítačový hardware a software

  • 2015
  • R
  • Link
Result

Synchronization Technique for TMR System After Dynamic Reconfiguration on FPGA

This paper presents the methods of design synchronization after the partial dynamic reconfiguration of FPGA and introduces a new method inspired from previous one which is still used. The implementation of this method on TMR fault t...

Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

  • 2013
  • D
Result

Accessory Tools for Partial Dynamic Reconfiguration on Xilinx FPGAs

This application note describes accessory tools for partial dynamic reconfiguration on Xilinx FPGAs. These accessory tools deal with insertion of bus-macros file that contains a module to be reconfigured. The idea is to rel...

JC - Počítačový hardware a software

  • 2007
  • A
Result

Reconfiguration Strategy for FPGA Dependability Characteristics Improvement based on Stochastic Petri Net

characteristics in a simple FPGA design with dynamically reconfigurable modules. Some parts of the design are not possible or proper to reconfigure dynamically (e.g. moduleThis paper shows the impact of the trade-...

JC - Počítačový hardware a software

  • 2009
  • D
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