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How to teach computer simulation and SPICE?
Experience of teaching the modeling and computer simulation of electronic circuits by means of netlist-based SPICE simulation is described.
JA - Elektronika a optoelektronika, elektrotechnika
- 2005 •
- D
Rok uplatnění
D - Stať ve sborníku
Universal schematic editor
it can be used for other applications such as the generation of a netlist, which can...
JA - Elektronika a optoelektronika, elektrotechnika
- 2002 •
- D
Rok uplatnění
D - Stať ve sborníku
Converter of the OrCAD and EEDraw Netlist Files to the CIA (Circuit Interactive Analyzer) Input Language Standard
A reliable converter of both EEDraw and OrCAD netlist files to the CIA (Circuit Interactive Analyzer) format has been created. The OrCAD's well-known graphic editor is one of the most frequently employed one, and exists in more Windows and n...
JA - Elektronika a optoelektronika, elektrotechnika
- 2011 •
- R •
- Link
Rok uplatnění
R - Software
Výsledek na webu
The Framework for Parallel Computing Systems Design
This paper presents a framework design solution for parallel computing digital systems design. The framework uses the Simulink software as a standard design entry tool. The key role in the Framework design plays the netlist compiler, which t...
JD - Využití počítačů, robotika a její aplikace
- 2004 •
- D
Rok uplatnění
D - Stať ve sborníku
Graphical Framework for Digital Design
tool is a netlist compiler, which transforms the graphical description as a standard design entry tool. This software together with a designed netlist compiler......
JD - Využití počítačů, robotika a její aplikace
- 2004 •
- D
Rok uplatnění
D - Stať ve sborníku
Graphical Framework for Digital Systems Design
In this paper a framework design solution for digital systems design is presented. The framework uses the Simulink software as a standard design entry tool. The key role in the Framework design plays the netlist compiler, which is a stand wi...
JD - Využití počítačů, robotika a její aplikace
- 2004 •
- D
Rok uplatnění
D - Stať ve sborníku
On Identification of XOR Gates in AIGs
In this paper we present a preliminary work, where XOR structures are identified in an AIG. We study how structural hashing in ABChandles XOR gates coming from an already mapped netlist, whether they are structurally retained and whether new...
JC - Počítačový hardware a software
- 2015 •
- D
Rok uplatnění
D - Stať ve sborníku
Testing PCBs Based on Boundary Scan
The paper describes a practical approach to testing PCBs with Xilinx FPGAs. The approach is based on a PCB netlist analysis, which is revealing the existing connections on the PCB through the Boundary Scan chain and comparing the two results...
JC - Počítačový hardware a software
- 2003 •
- D
Rok uplatnění
D - Stať ve sborníku
ALGORITHMS FOR APPROXIMATE SYMBOLIC ANALYSIS
. Small-signal models are computed automatically from Spice netlist. The system can...
JA - Elektronika a optoelektronika, elektrotechnika
- 2003 •
- D
Rok uplatnění
D - Stať ve sborníku
Simplified SPICE Model of TiO2 Memristor
to prevent exponential overflows during simulation. A full PSpice netlist is provided.
Electrical and electronic engineering
- 2015 •
- D •
- Link
Rok uplatnění
D - Stať ve sborníku
Výsledek na webu
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