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The Design of On-line Checkers and Their Use in Verification and Testing
In the article, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers for digital by an on-line checker of a digital component. It is d...
JC - Počítačový hardware a software
- 2009 •
- Jx
Rok uplatnění
Jx - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)
Design of FPGA-Based Dependable Systems
on automated generation of checkers in FPGA is presented. Dependability models of architectures based on the use of on-line checkers are described in the paper as well. First, theresults of our research in the area of on-<...
JC - Počítačový hardware a software
- 2008 •
- D
Rok uplatnění
D - Stať ve sborníku
Digital Systems Architectures Based on On-line Checkers
of hardware checkers is presented. It is
shown how the methodology can be used to generate on-line
checkers of communication protocols, counters, decoders,
registers, comparators, etc. It is also demonstrated how ...
JC - Počítačový hardware a software
- 2008 •
- D
Rok uplatnění
D - Stať ve sborníku
The Design of Hardware Checkers for Verification and Diagnostic Purposes
In the paper, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers of digital components. It is shown how PSL can be used to describe conditions to be checked by an on...
JC - Počítačový hardware a software
- 2008 •
- D
Rok uplatnění
D - Stať ve sborníku
Checker Design for On-line Testing of Xilinx FPGA Communication
In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemented in Xilinx FPGA based designs. A for...
JC - Počítačový hardware a software
- 2007 •
- D
Rok uplatnění
D - Stať ve sborníku
Checkers Design for Communication Protocols Based on FPGAs
In the paper, the principles of a unit design which can be used for on-line communication protocol checking is presented. It is shown how the checker can be used to check the communication between IP cores implemented in FPGA. The <...
JC - Počítačový hardware a software
- 2008 •
- D
Rok uplatnění
D - Stať ve sborníku
BPEL Checker
BPEL checker is a command-line tool for verification of BPEL code against session protocols. For a given web service implemented in the BPEL language (a BPEL script), the tool can check whether the BPEL script interacts with other s...
JC - Počítačový hardware a software
- 2007 •
- R •
- Link
Rok uplatnění
R - Software
Výsledek na webu
Automatic Construction of On-line Checking Circuits Based on Finite Automata
checker, introduces fault tolerance aspects to the unit. It provides the information about correctness of the unit output. Checkers are constructed from models inferred for automatic construction of online checkers has bee...
Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
- 2014 •
- D •
- Link
Rok uplatnění
D - Stať ve sborníku
Výsledek na webu
Checker for Communication Protocol between IP Cores Based on FPGA
In the paper, the principles of a unit design which can be used for on-line communication protocol checking is presented. It is shown how the checker can be used. From the description, the checker description in VHDL is gen...
JC - Počítačový hardware a software
- 2007 •
- D
Rok uplatnění
D - Stať ve sborníku
Lightweight Verification of Array Indexing
called the Index Checker. We evaluated the Index Checker on over 100,000 lines...
Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
- 2018 •
- D •
- Link
Rok uplatnění
D - Stať ve sborníku
Výsledek na webu
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