Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques.

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216224%3A14330%2F19%3A00107545" target="_blank" >RIV/00216224:14330/19:00107545 - isvavai.cz</a>

Alternative codes found

RIV/00216305:26230/19:PU134941

Result on the web

<a href="http://dx.doi.org/10.1109/TVLSI.2019.2923848" target="_blank" >http://dx.doi.org/10.1109/TVLSI.2019.2923848</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/TVLSI.2019.2923848" target="_blank" >10.1109/TVLSI.2019.2923848</a>

Result language

angličtina

Original language name

Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques.

Original language description

Randomness testing is an important procedure that bit streams, produced by critical cryptographic primitives such as encryption functions and hash functions, have to undergo. In this paper, a new hardware platform for the randomness testing is proposed. The platform exploits the principles of genetic programming, which is a machine learning technique developed for the automated program and circuit design. The platform is capable of evolving efficient randomness distinguishers directly on a chip. Each distinguisher is represented as a Boolean polynomial in the algebraic normal form. The randomness testing is conducted for bit streams that are either stored in an on-chip memory or generated by a circuit placed on the chip. The platform is developed with a Xilinx Zynq-7000 All Programmable System on Chip that integrates a field programmable gate array with on-chip ARM processors. The platform is evaluated in terms of the quality of randomness testing, performance, and resources utilization. With power budget less than 3 W, the platform provides comparable randomness testing capabilities with the standard testing batteries running on a personal computer.

Czech name

—

Czech description

—

Type

J_imp - Article in a specialist periodical, which is included in the Web of Science database

CEP classification

—

OECD FORD branch

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project

<a href="/en/project/GA16-08565S" target="_blank" >GA16-08565S: Advancing cryptanalytic methods through evolutionary computing</a><br>

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2019

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

ISSN

1063-8210

e-ISSN

1557-9999

Volume of the periodical

27

Issue of the periodical within the volume

12

Country of publishing house

US - UNITED STATES

Number of pages

11

Pages from-to

2734-2744

UT code for WoS article

000508360300004

EID of the result in the Scopus database

2-s2.0-85069509602