IndiRA: Design and Implementation of a Pipelined RISC-V Processor

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216275%3A25530%2F23%3A39921209" target="_blank" >RIV/00216275:25530/23:39921209 - isvavai.cz</a>
Result on the web
<a href="https://ieeexplore.ieee.org/document/10109058" target="_blank" >https://ieeexplore.ieee.org/document/10109058</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/RADIOELEKTRONIKA57919.2023.10109058" target="_blank" >10.1109/RADIOELEKTRONIKA57919.2023.10109058</a>

Result language
angličtina
Original language name
IndiRA: Design and Implementation of a Pipelined RISC-V Processor
Original language description
The development of Machine Learning and IoT technology requires fast processing. RISC-V is an open-source reduced instruction set-based instruction set architecture, and the processor based on this architecture can be modified accordingly. The base integer instruction extension supports the operating system environment and is also suitable for embedded systems. It is a 32-bit instruction extension and is defined as RV32I. In this paper, we propose a 32-bit integer instruction-based RISC-V processor core. The proposed core has a five-stage pipeline, including the optimized arithmetic and logic unit. The instruction fetch stage is merged with the pre-fetch stage dynamic branch prediction into a two-stage pipeline. The processor is implemented using Verilog HDL, and the resource utilization is verified for FPGA. The results show that the proposed module performs 30% better than the best-performing processor (considering operating frequency) and showed a 17.6% improvement in the proposed core.
Czech name
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Czech description
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Project
<a href="/en/project/EF17_049%2F0008394" target="_blank" >EF17_049/0008394: Cooperation in Applied Research between the University of Pardubice and companies, in the Field of Positioning, Detection and Simulation Technology for Transport Systems (PosiTrans)</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2023
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
33rd International Conference Radioelektronika, Radioelektronika 2023
ISBN
979-8-3503-9834-2
ISSN
—
e-ISSN
—
Number of pages
6
Pages from-to
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Publisher name
IEEE (Institute of Electrical and Electronics Engineers)
Place of publication
New York
Event location
Pardubice
Event date
Apr 19, 2023
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000990505700032

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