DESIGN AND DEVELOPMENT OF CONFIGURABLE PROCESSOR
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F10%3APU88288" target="_blank" >RIV/00216305:26220/10:PU88288 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
DESIGN AND DEVELOPMENT OF CONFIGURABLE PROCESSOR
Original language description
In this work the concept of design time configurable processor is introduced. The basic architecture of designed processor core and the basic instruction set. There are described minimal core configuration (integer core) its programming model and possible modifications which follow in to PTA (Packet Triggered Architecture).
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
PAD 2010
ISBN
978-80-214-4140-8
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
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Publisher name
VUT-FIT
Place of publication
Brno
Event location
Češkovice
Event date
Sep 13, 2010
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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