Design -Time Configurable Processor Basic Structure

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F10%3APU86536" target="_blank" >RIV/00216305:26220/10:PU86536 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Design -Time Configurable Processor Basic Structure
Original language description
In this work the concept of design time configurable processor is introduced. The basic architecture of designed processor core and the basic instruction set. There are described minimal core configuration (integer core) and its programming model. Processor tightly coupled peripheral like a Cache, Memory Management Unit, Protection Unit and Segment Unit are introduced. There are as well the proposed blocks for power management and power save modes. In the conclusion, the comparison between other similardesigns is outlined. There is summarized actual state of work and future work is proposed as well.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2010
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.
ISBN
978-1-4244-6610-8
ISSN
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e-ISSN
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Number of pages
2
Pages from-to
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Publisher name
Vienna University of Technology, Austria
Place of publication
Vienna, Austria
Event location
Vienna
Event date
Apr 14, 2010
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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