VHDL RT Level Parser/Analyser of a Source Code

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F00%3APU28630" target="_blank" >RIV/00216305:26220/00:PU28630 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
VHDL RT Level Parser/Analyser of a Source Code
Original language description
During our research activities in the field of testability analysis it was revealed that it is reasonable to perform the algorithms not on the VHDL source file, but rather on "an useable database" which reflects the structure of the circuit under analysis and the diagnostic features of the elements and connections between them. For this purpose an interface between VHDL source text and the software performing the analysis was defined. The paper deals with a special parser/analyser that accepts a subsetof the IEEE Standard 1076 Hardware Description Language oriented to description of digital circuits on RT level of modelling. The parser/analyser produces a special database of four mutually depending files that is suitable for testability analysis.
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F98%2F1463" target="_blank" >GA102/98/1463: Methodology and tools for digital circuits testability analysis</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2000
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the fourth international scientific conference Electronic Computers & Informatics'2000
ISBN
80-88922-25-9
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
150-155
Publisher name
Faculty of Electrical Engineering and Informatics, University of Technology Košice
Place of publication
Košice
Event location
Košice
Event date
Nov 30, 1999
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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