Two Level Testability System

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F01%3APU28700" target="_blank" >RIV/00216305:26220/01:PU28700 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Two Level Testability System
Original language description
Principles of two level testability analysis system will are described in the paper. The behavioural description of the unit under analysis (UUA) is the first level, on which the source VHDL file is taken as an input. On this level, the VHDL constructions which might cause testability problems in the resulting design are identified and the possibility of deriving i paths is evaluated. The RT level is the second level, on which the testability aspects are taken into account. For these purposes, the RT leevel structure is converted into a directed labelled graph which reflects the structure of the UUA and its diagnostic features which are important for the testability analysis. The analysis is done on the graph instead of on the VHDL source text.
Czech name
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Czech description
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Project
<a href="/en/project/GA102%2F01%2F1531" target="_blank" >GA102/01/1531: Formal approaches in digital circuit diagnostics - testable design verification</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2001
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 35th Spring International Conference MOSIS'01
ISBN
80-85988-57-7
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
433-440
Publisher name
Neuveden
Place of publication
Ostrava
Event location
Hradec nad Moravicí
Event date
May 9, 2001
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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