Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F01%3APU28672" target="_blank" >RIV/00216305:26220/01:PU28672 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Optimizing SW/HW Architecture for Parallel Embedded Systems - A Case Study
Original language description
The paper addresses the issue of prototyping hw/sw architecture of application-specific multi-processor systems (recently on a chip). Performance prediction of these systems, either bus-based SMPs or message-passing networks of DSPs, is undertaken usinga CSP-based tool Transim. Variations in processor count, clock rate, link speed, bus bandwidth, cache line, as well as in partitioning and mapping the resulting sw components to processors can be easily accounted for. The technique is demonstrated on pparallel FFT on 2 to 8 processors.
Czech name
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Czech description
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Publication year
2001
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the the International Workshop on Discrete-Event System Design, DESDes'01
ISBN
83-85911-62-6
ISSN
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e-ISSN
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Number of pages
6
Pages from-to
103-108
Publisher name
Publishing House of Zielona Gora Technical University
Place of publication
Przytok near Zielona Gora, POLAND
Event location
Przytok near Zielona Gora
Event date
Nov 30, 2000
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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