RSD Algorithm Implementation to Semiflash ADC
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F04%3APU44406" target="_blank" >RIV/00216305:26220/04:PU44406 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
RSD Algorithm Implementation to Semiflash ADC
Original language description
RSD algorithm was implemented to cycles or pipelined switched-current analog-to-digital converter (ADC), where resolution of sub-converter is 1,5 bit. This implementation is well known. Implementation of RSD algorithm to ADC with 2,5-bit sub-converterispresented in this paper. The most critical blocs in classical ADC are reference currents sources and comparators. Usage of this algorithm decrease inaccuracy of these blocks impact on accuracy of full ADC.
Czech name
Implementace agoritmu RSD do semiflash ADC
Czech description
RSD algoritmus je implementován do cyklického nebo algoritmického převodníku AD se spínanými proudy. Tato implementace je známa. Tato implementace, kde dílčí převodník je 2,5-bitový je nová.
Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2004
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the WSEAS Conferences, Rio de Janeiro, Brasil 2004
ISBN
960-8457-03-3
ISSN
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e-ISSN
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Number of pages
3
Pages from-to
205-207
Publisher name
WSEAS
Place of publication
Rio de Janeiro
Event location
Rio de Janeiro
Event date
Oct 12, 2004
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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