RSD Algorithm Implementation to Semiflash ADC

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F04%3APU44783" target="_blank" >RIV/00216305:26220/04:PU44783 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

RSD Algorithm Implementation to Semiflash ADC

Original language description

RSD algorithm was implemented to cycles or pipelined switched-current analog-to-digital converter (ADC), where resolution of sub-converter is 1,5 bit. This implementation is well known. Implementation of RSD algorithm to ADC with 2,5-bit sub-converterispresented in this paper. The most critical blocs in classical ADC are reference currents sources and comparators. Usage of this algorithm decrease inaccuracy of these blocks impact on accuracy of full ADC.

Czech name

Implementace RSD algoritmu do převodníku AD typu semiflash

Czech description

RSD algoritmus je implementován do cyklického nebo algoritmického převodníku AD se spínanými proudy. Tato implementace je známa. Tato implementace, kde dílčí převodník je 2,5-bitový je nová.

Type

J_x - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)

CEP classification

JA - Electronics and optoelectronics

OECD FORD branch

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Project

Result was created during the realization of more than one project. More information in the Projects tab.

Continuities

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year

2004

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

WSEAS Transactions on Circuits

ISSN

1109-2734

e-ISSN

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Volume of the periodical

2004

Issue of the periodical within the volume

9

Country of publishing house

GR - GREECE

Number of pages

3

Pages from-to

1971-1973

UT code for WoS article

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EID of the result in the Scopus database

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