DIGITAL PHASE-LOCKED LOOP FOR DATA CLOCK RECOVERY SYSTEM

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F09%3APU78912" target="_blank" >RIV/00216305:26220/09:PU78912 - isvavai.cz</a>

Result on the web

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DOI - Digital Object Identifier

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Result language

angličtina

Original language name

DIGITAL PHASE-LOCKED LOOP FOR DATA CLOCK RECOVERY SYSTEM

Original language description

This application note contains detail description and implementation of digital phase-locked loop (for short DPLL) designed by using VHSIC hardware description language (for short VHDL). This programming language was developed for hardware design of microchips and digital circuits, later adapted for programming FPGA and CPLD circuits. FPGAs and CPLDs are very useful for making design models, so we are able to test the design before fabrication. DPLL is analogous to PLL constructed from analog electroniccomponents. Wide usage (FM demodulation, FSK demodulation, tone decoding, frequency multiplication, clock synchronization) makes from DPLL or PLL important electronic component in signal processing and digital systems. Design described in this paper wasused as clock recovery and input data synchronization system by implementation of USB protocol into FPGA circuit again by using VHD language.

Czech name

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Czech description

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Type

D - Article in proceedings

CEP classification

JA - Electronics and optoelectronics

OECD FORD branch

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Project

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Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year

2009

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection

Electronic Devices and Systems EDS 08

ISBN

978-80-214-3717-3

ISSN

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e-ISSN

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Number of pages

7

Pages from-to

383-389

Publisher name

Ing. Zdeněk Novotný

Place of publication

Brno

Event location

Brno

Event date

Sep 2, 2009

Type of event by nationality

WRD - Celosvětová akce

UT code for WoS article

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