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ČeštinaEnglish

Design and Characteristics of Digital Locked Loops

Result description

An analysis of discrete phase locked loop (DPLL) or discrete delay locked loop (DDLL) and methods determining their characteristics based on analog template are performed in this paper. There are derived transfer responses and error function for the 1storder and 2nd order digital loops with closed-form expressions. Two ways and equations for the loop filter parameters setting for the 2nd order DPLL is presented too.

Keywords

Coherent receiverSoftware defined radioCarrier synchronizationSymbol timingLocked loop

The result's identifiers

Alternative languages

  • Result language

    angličtina

  • Original language name

    Design and Characteristics of Digital Locked Loops

  • Original language description

    An analysis of discrete phase locked loop (DPLL) or discrete delay locked loop (DDLL) and methods determining their characteristics based on analog template are performed in this paper. There are derived transfer responses and error function for the 1storder and 2nd order digital loops with closed-form expressions. Two ways and equations for the loop filter parameters setting for the 2nd order DPLL is presented too.

  • Czech name

    —

  • Czech description

    —

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JA - Electronics and optoelectronics

  • OECD FORD branch

    —

Result continuities

  • Project

    Result was created during the realization of more than one project. More information in the Projects tab.

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
    Z - Vyzkumny zamer (s odkazem do CEZ)

Others

  • Publication year

    2009

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of the 2nd WSEAS International Conference Sensors and Signals

  • ISBN

    978-960-474-135-9

  • ISSN

    —

  • e-ISSN

    —

  • Number of pages

    4

  • Pages from-to

    —

  • Publisher name

    WSEAS Press

  • Place of publication

    Baltimore, USA

  • Event location

    Baltimore

  • Event date

    Nov 7, 2009

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    —

Basic information

Result type

D - Article in proceedings

D

CEP

JA - Electronics and optoelectronics

Year of implementation

2009

Similar results(10)

Experimental evaluation of voltage synchronization algorithmsDIGITAL PHASE-LOCKED LOOP FOR DATA CLOCK RECOVERY SYSTEMDiscrete-time Phase and Delay Locked Loops Analyses in Tracking Mode