All

What are you looking for?

All
Projects
Results
Organizations

Quick search

  • Projects supported by TA ČR
  • Excellent projects
  • Projects with the highest public support
  • Current projects

Smart search

  • That is how I find a specific +word
  • That is how I leave the -word out of the results
  • “That is how I can find the whole phrase”

Application of FMEA Procedure for ALU Unit Testing

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F11%3APU93206" target="_blank" >RIV/00216305:26220/11:PU93206 - isvavai.cz</a>

  • Result on the web

  • DOI - Digital Object Identifier

Alternative languages

  • Result language

    čeština

  • Original language name

    Application of FMEA Procedure for ALU Unit Testing

  • Original language description

    Arithmetic-logic unit (ALU) is an important part of each microprocessor and its main purpose is to process arithmetical and logical operations. Correct results of these calculations are crucial for performance of the entire processor unit. Thus thoroughtesting of all functions before deployment is necessary. Also thorough testing of whole system is crucial for correct system performance during the life cycle. Following article describes proposal of algorithm to test basic arithmetical-logical instructions and analysis of each gate by the FMEA (Failure mode and effect analysis) method.

  • Czech name

    Application of FMEA Procedure for ALU Unit Testing

  • Czech description

    Arithmetic-logic unit (ALU) is an important part of each microprocessor and its main purpose is to process arithmetical and logical operations. Correct results of these calculations are crucial for performance of the entire processor unit. Thus thoroughtesting of all functions before deployment is necessary. Also thorough testing of whole system is crucial for correct system performance during the life cycle. Following article describes proposal of algorithm to test basic arithmetical-logical instructions and analysis of each gate by the FMEA (Failure mode and effect analysis) method.

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

  • Continuities

    S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2011

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    34th International Conference on Telecommunications and Signal Processing (TSP 2011)

  • ISBN

    978-1-4577-1409-2

  • ISSN

  • e-ISSN

  • Number of pages

    5

  • Pages from-to

    1-5

  • Publisher name

    Neuveden

  • Place of publication

    Neuveden

  • Event location

    Budapest

  • Event date

    Aug 18, 2011

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article