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System on Chip Design of a Linear System Solver

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F14%3A00224196" target="_blank" >RIV/68407700:21240/14:00224196 - isvavai.cz</a>

  • Result on the web

    <a href="http://dx.doi.org/10.1109/ISSOC.2014.6972445" target="_blank" >http://dx.doi.org/10.1109/ISSOC.2014.6972445</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/ISSOC.2014.6972445" target="_blank" >10.1109/ISSOC.2014.6972445</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    System on Chip Design of a Linear System Solver

  • Original language description

    This paper is focused on hardware error-free solution of dense linear systems using residual arithmetic on a System on Chip Modular System. The designed Modular System uses Residual Processors (RP)s for solving independent linear systems in residue arithmetic and combines RP solutions into solution of the linear system. A System on Chip architecture of the Modular System with several RPs is designed, each with a large memory unit used for data transfer and storage. A Xilinx FPGA architecture with a MicroBlaze processor is used to verify the proposed architecture. The experimental results are obtained for an evaluation FPGA board with Virtex 6 and a 1GiB DDR memory and serve for further theoretical analysis of the system performance for various linear system sizes and the architecture of the system.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

    <a href="/en/project/GAP103%2F12%2F2377" target="_blank" >GAP103/12/2377: Study of properties of residual arithmetic for solving sets of linear equations</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2014

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    2014 International Symposium on System-on-Chip Proceedings

  • ISBN

    9781479968909

  • ISSN

  • e-ISSN

  • Number of pages

    6

  • Pages from-to

  • Publisher name

    IEEE

  • Place of publication

    Piscataway

  • Event location

    Tampere

  • Event date

    Oct 28, 2014

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article

    000356507900017