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Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F13%3A00209154" target="_blank" >RIV/68407700:21240/13:00209154 - isvavai.cz</a>

  • Result on the web

    <a href="http://dx.doi.org/10.1109/DSD.2013.125" target="_blank" >http://dx.doi.org/10.1109/DSD.2013.125</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/DSD.2013.125" target="_blank" >10.1109/DSD.2013.125</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver

  • Original language description

    Residual processor (RP) is a dedicated hardware for solution of sets of linear congruences. RPs are parts of a larger modular system for error-free solution of linear equations in residue arithmetic. We present new FPGA and ASIC RP implementations, focusing mainly on their memory units being a bottleneck of the calculation and therefore determining the efficiency of the system. First, we choose an FPGA to easily test the functionality of our implementation, then we do the same in ASIC, and finally we compare both implementations together. The experimental FPGA results are obtained for Xilinx Virtex 6, while the ASIC results are obtained from Synopsys tools with a 130 nm standard cell library. Results also present a maximum matrix dimension fitting directly into the FPGA and achieved speed as a function of the dimension.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

    JC - Computer hardware and software

  • OECD FORD branch

Result continuities

  • Project

    <a href="/en/project/GAP103%2F12%2F2377" target="_blank" >GAP103/12/2377: Study of properties of residual arithmetic for solving sets of linear equations</a><br>

  • Continuities

    P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Others

  • Publication year

    2013

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of 16th Euromicro Conference on Digital System Design

  • ISBN

    978-0-7695-5074-9

  • ISSN

  • e-ISSN

  • Number of pages

    4

  • Pages from-to

    284-287

  • Publisher name

    IEEE Service Center

  • Place of publication

    Piscataway

  • Event location

    Santander

  • Event date

    Sep 4, 2013

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article