Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F12%3A00197211" target="_blank" >RIV/68407700:21240/12:00197211 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/ICECS.2012.6463632" target="_blank" >http://dx.doi.org/10.1109/ICECS.2012.6463632</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ICECS.2012.6463632" target="_blank" >10.1109/ICECS.2012.6463632</a>
Alternative languages
Result language
angličtina
Original language name
Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA
Original language description
The residual processor is a dedicated hardware for solving sets of linear congruences. It is a part of the modular system for solving sets of linear equations without rounding errors using Residue Number System. We present a new FPGA implementation of the residual processor, focusing mainly on the memory unit that forms a bottleneck of the calculation, and therefore determines the effectivity of the system. FPGA has been chosen, as it allows us to optimally implement the designed architecture dependingon the size of the problem. The proposed memory architecture of the modular system is implemented using the internal FPGA block RAM. Experimental results are obtained for the Xilinx Virtex 6 family. Results present the maximum matrix dimension fitting directly into the FPGA, and achieved speed as a function of the dimension.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
IN - Informatics
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GAP103%2F12%2F2377" target="_blank" >GAP103/12/2377: Study of properties of residual arithmetic for solving sets of linear equations</a><br>
Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace
Others
Publication year
2012
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
The 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012
ISBN
978-1-4673-1261-5
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
689-692
Publisher name
IEEE Circuits and Systems Society
Place of publication
Monterey
Event location
Seville
Event date
Dec 9, 2012
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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