System Design of an FPGA Linear Solver

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F14%3A00219269" target="_blank" >RIV/68407700:21240/14:00219269 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
System Design of an FPGA Linear Solver
Original language description
The work is focused on design of a Modular System performing error-free solution of dense linear systems using residue arithmetic in Xilinx FPGA. The designed system shall use a set of Residual Processors (RP)s for linear system solution in Residue Number System and reconstruct the set's solution afterwards. The currently proposed system's architecture has a single RP, a large DDR memory used for data transfer in between a PC and the system, and a built-in MicroBlaze processor. Future work will focus onextending the architecture to implement the entire Modular System consisting of multiple RPs and performing the backward transformation from residue representation into the rational number set.
Czech name
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Czech description
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Project
<a href="/en/project/GAP103%2F12%2F2377" target="_blank" >GAP103/12/2377: Study of properties of residual arithmetic for solving sets of linear equations</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2014
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the Work in Progress Session held in connection with the 40th EUROMICRO Conference on Software Engineering and Advanced Applications and the 17th EUROMICRO Conference on Digital System Design
ISBN
978-3-902457-40-0
ISSN
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e-ISSN
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Number of pages
2
Pages from-to
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Publisher name
Johannes Kepler University
Place of publication
Linz
Event location
Verona
Event date
Aug 27, 2014
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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