SYMBOLIC ANALYSIS OF TRANSISTOR-LEVEL CIRCUITS

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F12%3APU100427" target="_blank" >RIV/00216305:26220/12:PU100427 - isvavai.cz</a>
Alternative codes found
RIV/60162694:G43__/12:00478011
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
SYMBOLIC ANALYSIS OF TRANSISTOR-LEVEL CIRCUITS
Original language description
The paper deals with the implementation of symbolic analysis of transistor-level circuits in the symbolic simulator Snap. The program is characterized by several unique features. All models are stored in a text-based library, which can be easily extendedby user. To be able to analyze moderate size circuits two algorithms of approximate symbolic analysis are implemented. The first algorithm simplifies the circuit model and the second one simplifies the generated formula. This paper describes a procedurefor automated extraction of small-signal models of semiconductor devices from the output file of the PSpice simulator.
Czech name
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Czech description
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Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Publication year
2012
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the INTERNATIONAL SCIENTIFIC CONFERENCE NEW TRENDS IN SIGNAL PROCESSING 2012 (NTSP 2012)
ISBN
978-80-8040-447-5
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
79-82
Publisher name
AOS
Place of publication
Liptovský Mikuláš, Slovakia
Event location
Tatranské Zruby
Event date
May 16, 2012
Type of event by nationality
EUR - Evropská akce
UT code for WoS article
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