The FPGA Implementation of Dictionary; HW Consumption Versus Latency
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F13%3APU104212" target="_blank" >RIV/00216305:26220/13:PU104212 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
The FPGA Implementation of Dictionary; HW Consumption Versus Latency
Original language description
This paper presents a study on the possibilities of dictionary implementation for a dictionary compression system in FPGA. The possibilities of creation of the dictionary using the registers and the RAM memory are described. For these implementations, the interdependence of hardware consumption and latency during basic dictionary processes like writing, reading and searching a match is described. With regard to the hardware consumption, RAM dictionary implementation is the most effective. On the contrary, dictionary implementation by the registers is more suitable with regard to the latency during searching the matches in the dictionary. For these reasons, the combination of both implementation approaches was implemented. The core of the dictionary isin RAM memory and the searching part is implemented by the registers. This part is similar to a hash table. It is implemented by the parallel shift registers to minimize the searching latency.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2013
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of The 36th International Conference on Telecommunications and Signal Processing
ISBN
978-1-4799-0403-7
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
82-86
Publisher name
Neuveden
Place of publication
Neuveden
Event location
Rome
Event date
Jul 2, 2013
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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