Design of a High-Throughput Match Search Unit for Lossless Compression Algorithms

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F19%3A10133189" target="_blank" >RIV/63839172:_____/19:10133189 - isvavai.cz</a>
Alternative codes found
RIV/68407700:21240/19:00326313
Result on the web
<a href="http://dx.doi.org/10.1109/CCWC.2019.8666521" target="_blank" >http://dx.doi.org/10.1109/CCWC.2019.8666521</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/CCWC.2019.8666521" target="_blank" >10.1109/CCWC.2019.8666521</a>

Result language
angličtina
Original language name
Design of a High-Throughput Match Search Unit for Lossless Compression Algorithms
Original language description
This paper presents an attempt to combine recent research in fields of hardware-and software-based high-throughput universal lossless compression algorithms and their implementations, resulting into a case study focusing on one of the most critical parts of compression algorithms - a Match Search Unit (MSU) and its parallelization. The presented FPGA design combines ideas of the LZ4 algorithm (which is derived from the most common LZ77) with the state of the art hardware architectures for lossless compression also based on LZ77. This approach might lead to a smaller, better organized or more efficient "building block" for modern implementations of hardware driven lossless compression algorithms. The presented design focuses on optimization of the main problem of the LZ77 family, namely the construction of and searching in a compression dictionary. Particularly, we combine a Live Value Table (LVT) with multi-ported memory in order to improve the bandwidth of the dictionary and the Fibonacci hashing principle originating from LZ4 algorithm to decrease latency of the MSU and to achieve overall higher throughput rate. For the design synthesis an FPGA of the Xilinx Virtex-7 family was used.
Czech name
—
Czech description
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Type
D - Article in proceedings
CEP classification
—
OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Project
<a href="/en/project/EF16_013%2F0001797" target="_blank" >EF16_013/0001797: CESNET E-Infrastructure - Modernisation</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2019
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
2019 IEEE 9TH ANNUAL COMPUTING AND COMMUNICATION WORKSHOP AND CONFERENCE (CCWC)
ISBN
978-1-72810-554-3
ISSN
—
e-ISSN
—
Number of pages
7
Pages from-to
732-738
Publisher name
IEEE
Place of publication
Las Vegas, NV, USA
Event location
Las Vegas, NV, USA
Event date
Jan 7, 2019
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000469462800120

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