LZ4 Compression Algorithm on FPGA

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F15%3A00234916" target="_blank" >RIV/68407700:21240/15:00234916 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/ICECS.2015.7440278" target="_blank" >http://dx.doi.org/10.1109/ICECS.2015.7440278</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ICECS.2015.7440278" target="_blank" >10.1109/ICECS.2015.7440278</a>

Result language
angličtina
Original language name
LZ4 Compression Algorithm on FPGA
Original language description
This paper describes analysis and implementation of a LZ4 compression algorithm. LZ4 is derived from a standard LZ77 compression algorithm and is focused on the compression and decompression speed. The LZ4 lossless compression algorithm was analyzed regarding its suitability for hardware implementation. The first step of this research is based on software implementation of LZ4 with regard to the future hardware implementation. As a second step, a simple hardware implementation of LZ4 is evaluated for bottlenecks in the original LZ4 code. Xilinx Virtex?6 and 7?Series FPGAs are used to obtain experimental results. These results are compared to the industry competitor.
Czech name
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Czech description
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Publication year
2015
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
21st IEEE International Conference on Electronics, Circuits, and Systems
ISBN
978-1-4799-2451-6
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
179-182
Publisher name
Institute of Electrical and Electronics Engineers
Place of publication
New York
Event location
Cairo
Event date
Dec 6, 2015
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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