High Throughput and Low Latency LZ4 Compressor on FPGA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F19%3A10133252" target="_blank" >RIV/63839172:_____/19:10133252 - isvavai.cz</a>
Alternative codes found
RIV/68407700:21240/19:00335424
Result on the web
<a href="http://dx.doi.org/10.1109/ReConFig48160.2019.8994794" target="_blank" >http://dx.doi.org/10.1109/ReConFig48160.2019.8994794</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ReConFig48160.2019.8994794" target="_blank" >10.1109/ReConFig48160.2019.8994794</a>
Alternative languages
Result language
angličtina
Original language name
High Throughput and Low Latency LZ4 Compressor on FPGA
Original language description
This paper presents an FPGA design implementing a single LZ4 lossless compression IP block, providing a throughput of 6 Gbps combined with extremely low latency, while still retaining full binary compatibility with the original LZ4 format. The best-known competitor is capable of processing up to 2 Gbps per block/engine with unknown latency. The presented design uses two key features: a low-latency 8-way match search unit and consequently a match buffer which allows encoding LZ4 sequences independently to reduce stalls in the data processing pipeline. The design was evaluated on several compression corpora with an average compression ratio of 1.7.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
<a href="/en/project/EF16_013%2F0001797" target="_blank" >EF16_013/0001797: CESNET E-Infrastructure - Modernisation</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2019
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2019 International Conference on ReConFigurable Computing and FPGAs
ISBN
978-1-72811-957-1
ISSN
2640-0472
e-ISSN
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Number of pages
5
Pages from-to
5
Publisher name
IEEE
Place of publication
Piscataway , USA
Event location
Cancún, Mexiko
Event date
Dec 9, 2019
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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