Design of the 16bit Delta Sigma Converter for Sensor Signal Processing

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F14%3APU112147" target="_blank" >RIV/00216305:26220/14:PU112147 - isvavai.cz</a>
Result on the web
—
DOI - Digital Object Identifier
—

Result language
angličtina
Original language name
Design of the 16bit Delta Sigma Converter for Sensor Signal Processing
Original language description
The paper deals with a design of the 16-bit MASH Delta-sigma converter utilizing switched capacitor technique (SC). The attention was paid to reach 16bit of ENOB resolution even the same precision of STF in band. This requirement is crucial to evaluation of the signal amplitude independently on its frequency. Multistage structure of two second order CIDIDF modulator was used. The system consists of continuous time amplifier, switched Delta-sigma modulator and decimation digital filter. The ONSemi I3T25 350nm CMOS technology was used for the design. The value of SNDR = 106.5 dB (ENOB = 17.4 bits) was achieved.
Czech name
—
Czech description
—

Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2014
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
37th Internation Conference on Telecommunications and Signal Processing
ISBN
978-80-214-4983-1
ISSN
—
e-ISSN
—
Number of pages
4
Pages from-to
100-104
Publisher name
Neuveden
Place of publication
Berlín
Event location
Berlín
Event date
Jul 1, 2014
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
—

Similar results(10)