Instruction mapping process on the VLIW architectures
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F16%3APU118931" target="_blank" >RIV/00216305:26220/16:PU118931 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
Instruction mapping process on the VLIW architectures
Original language description
This paper deals with the process of instruction mapping on the digital signal processors. This process is used by the newly developed tool, which is designed for generating low-level assembly code for very long instruction word processors. The tool is suitable for creating cores of the signal processing algorithms.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JA - Electronics and optoelectronics
OECD FORD branch
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Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 22nd conference Student EEICT
ISBN
978-80-214-5350-0
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
385-389
Publisher name
Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
Place of publication
Brno
Event location
Brno
Event date
Apr 28, 2016
Type of event by nationality
CST - Celostátní akce
UT code for WoS article
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