A Fully Balanced Four-Terminal Floating Nullor for Ultra-Low Voltage Analog Filter Design
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F17%3APU120687" target="_blank" >RIV/00216305:26220/17:PU120687 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1049/iet-cds.2016.0212" target="_blank" >http://dx.doi.org/10.1049/iet-cds.2016.0212</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1049/iet-cds.2016.0212" target="_blank" >10.1049/iet-cds.2016.0212</a>
Alternative languages
Result language
angličtina
Original language name
A Fully Balanced Four-Terminal Floating Nullor for Ultra-Low Voltage Analog Filter Design
Original language description
This paper presents a new CMOS structure for a fully balanced four-terminal floating nullor (FBFTFN) which is suitable for ultra-low-voltage and low-power applications. This structure employs a bulk-driven quasi-floating-gate (BD-QFG) MOS transistor technique to provide the capability of ultra-low voltage, low-power operations as well as extended input voltage range. The functionality of the proposed circuits is demonstrated through simulations using SPICE and TSMC 0.18 um n-well CMOS technology with supply voltage of 0.5 V and dissipation power of 9.4 uW. To confirm the attractive features of the proposed circuit, the fully balanced filters such as band-pass Sallen-Key filter, voltage-mode universal biquadratic filter and current-mode sixth-order low-pass filter using proposed BD-QFG FBFTFN as active elements have been designed.
Czech name
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Czech description
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Classification
Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
20201 - Electrical and electronic engineering
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Name of the periodical
IET Circuits, Devices and Systems
ISSN
1751-858X
e-ISSN
1751-8598
Volume of the periodical
2017 (11)
Issue of the periodical within the volume
2, IF: 1.092
Country of publishing house
GB - UNITED KINGDOM
Number of pages
10
Pages from-to
173-182
UT code for WoS article
000398049800008
EID of the result in the Scopus database
2-s2.0-85015009016