Fully-balanced four-terminal floating nullor for ultra-low voltage analogue filter design
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21460%2F17%3A00320883" target="_blank" >RIV/68407700:21460/17:00320883 - isvavai.cz</a>
Result on the web
<a href="http://mr.crossref.org/iPage?doi=10.1049%2Fiet-cds.2016.0212" target="_blank" >http://mr.crossref.org/iPage?doi=10.1049%2Fiet-cds.2016.0212</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1049/iet-cds.2016.0212" target="_blank" >10.1049/iet-cds.2016.0212</a>
Alternative languages
Result language
angličtina
Original language name
Fully-balanced four-terminal floating nullor for ultra-low voltage analogue filter design
Original language description
This study presents a new complementary metal-oxide-semiconductor (CMOS) structure for a fully balanced four-terminal floating nullor (FBFTFN) which is suitable for ultra-low-voltage and low-power applications. This structure employs a bulk-driven quasi-floating-gate (BD-QFG) metal-oxide-semiconductor transistor technique to provide the capability of ultra-low-voltage, low-power operations as well as extended input voltage range. The functionality of the proposed circuits is demonstrated through simulations using SPICE and TSMC 0.18 mu m n-well CMOS technology with supply voltage of 0.5 V and dissipation power of 9.4 mu W. To confirm the attractive features of the proposed circuit, the fully balanced filters such as band-pass Sallen-Key filter, voltage-mode universal biquadratic filter and current-mode sixth-order low-pass filter using proposed BD-QFG FBFTFN as active elements have been designed.
Czech name
—
Czech description
—
Classification
Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
—
OECD FORD branch
20201 - Electrical and electronic engineering
Result continuities
Project
—
Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace
Others
Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Name of the periodical
IET Circuits, Devices & Systems
ISSN
1751-858X
e-ISSN
1751-8598
Volume of the periodical
11
Issue of the periodical within the volume
2
Country of publishing house
GB - UNITED KINGDOM
Number of pages
10
Pages from-to
173-182
UT code for WoS article
000398049800008
EID of the result in the Scopus database
—