High-Speed anomaly detection system using entropy calculation on FPGA
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F17%3APU123414" target="_blank" >RIV/00216305:26220/17:PU123414 - isvavai.cz</a>
Result on the web
<a href="http://eeict.feec.vutbr.cz/2017/sbornik/EEICT_2017-sbornik-komplet-2.pdf" target="_blank" >http://eeict.feec.vutbr.cz/2017/sbornik/EEICT_2017-sbornik-komplet-2.pdf</a>
DOI - Digital Object Identifier
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Alternative languages
Result language
angličtina
Original language name
High-Speed anomaly detection system using entropy calculation on FPGA
Original language description
This article discusses the use of entropy calculation on Field Programmable Gate Array (FPGA) for identifying anomalies in data communication. The article is focused on three type of entropy and described hardware-accelerated network card based on field programmable gate array, concretely NFB-40G2 card using the NetCOPE development platform and its properties.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture
Result continuities
Project
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Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 23rd Conference STUDENT EEICT 2017
ISBN
978-80-214-5496-5
ISSN
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e-ISSN
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Number of pages
5
Pages from-to
415-419
Publisher name
Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
Place of publication
Brno
Event location
Brno
Event date
Apr 27, 2017
Type of event by nationality
CST - Celostátní akce
UT code for WoS article
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