Hardware-Accelerated Twofish Core for FPGA

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F18%3APU128495" target="_blank" >RIV/00216305:26220/18:PU128495 - isvavai.cz</a>
Result on the web
<a href="http://tsp.vutbr.cz/datas/tsp2018_proc/TSP2018.pdf" target="_blank" >http://tsp.vutbr.cz/datas/tsp2018_proc/TSP2018.pdf</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/TSP.2018.8441386" target="_blank" >10.1109/TSP.2018.8441386</a>

Result language
angličtina
Original language name
Hardware-Accelerated Twofish Core for FPGA
Original language description
This article describes the hardware-accelerated implementation of the Twofish encryption algorithm on Field Programmable Gate Array (FPGA) network cards. The encryption core was implemented using the Virtex 7 network card to achieve real-time encryption and decryption. The algorithm was implemented for 128-bit words and 128-bit keys. This article demonstrates that the Twofish encryption core can operate with the maximum clock frequencies of 315MHz and achieves the throughput of 48 Gbps, which is faster than most currently implemented systems.
Czech name
—
Czech description
—

Project
<a href="/en/project/VI20162018036" target="_blank" >VI20162018036: Cryptographic privacy protection in 100GbE networks</a><br>
Continuities
S - Specificky vyzkum na vysokych skolach

Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
2018 41st International Conference on Telecommunications and Signal Processing (TSP)
ISBN
978-1-5386-4695-3
ISSN
1805-5435
e-ISSN
—
Number of pages
836
Pages from-to
338-341
Publisher name
Neuveden
Place of publication
Atény, Řecko
Event location
Athens, Greece
Event date
Jul 4, 2018
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000454845100076

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