Low-voltage Fully Differential Difference Transconductance Amplifier
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F18%3APU123700" target="_blank" >RIV/00216305:26220/18:PU123700 - isvavai.cz</a>
Alternative codes found
RIV/68407700:21460/18:00329560
Result on the web
<a href="http://dx.doi.org/10.1049/iet-cds.2017.0057" target="_blank" >http://dx.doi.org/10.1049/iet-cds.2017.0057</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1049/iet-cds.2017.0057" target="_blank" >10.1049/iet-cds.2017.0057</a>
Alternative languages
Result language
angličtina
Original language name
Low-voltage Fully Differential Difference Transconductance Amplifier
Original language description
A new complementary metal–oxide–semiconductor (CMOS) structure for fully differential difference transconductance amplifier (FDDTA) is presented in this study. Thanks to using the non-conventional quasi-floating-gate (QFG) technique the circuit is capable to work under low-voltage supply of 0.6 V with extended input voltage range and with class AB output stages. The QFG multiple-input metal–oxide–semiconductor transistor is used to reduce the count of the differential pairs that needed to realise the FDDTA with simple CMOS structure. The static power consumption of the proposed FDDTA is 40 uW. The FDDTA was designed in Cadence platform using 0.18 um CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC). As an example of applications a three-stage quadrature oscillator and fifth-order elliptic low-pass filter are presented to confirm the attractive features of the proposed CMOS structure of the FDDTA.
Czech name
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Czech description
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Classification
Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
—
OECD FORD branch
20201 - Electrical and electronic engineering
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Name of the periodical
IET Circuits, Devices and Systems
ISSN
1751-858X
e-ISSN
1751-8598
Volume of the periodical
12
Issue of the periodical within the volume
1, IF: 1.395
Country of publishing house
GB - UNITED KINGDOM
Number of pages
9
Pages from-to
73-81
UT code for WoS article
000419402700010
EID of the result in the Scopus database
2-s2.0-85040175641