All-Pass Time Delay Circuit Magnitude Response Optimization Using Fractional-Order Capacitor
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F18%3APU128602" target="_blank" >RIV/00216305:26220/18:PU128602 - isvavai.cz</a>
Result on the web
<a href="https://ieeexplore.ieee.org/document/8624059" target="_blank" >https://ieeexplore.ieee.org/document/8624059</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/MWSCAS.2018.8624059" target="_blank" >10.1109/MWSCAS.2018.8624059</a>
Alternative languages
Result language
angličtina
Original language name
All-Pass Time Delay Circuit Magnitude Response Optimization Using Fractional-Order Capacitor
Original language description
Paper presents the integer- and fractional-order cases of a voltage-mode all-pass time delay circuit, or more frequently called as all-pass filter, employing a single negative-type current-controlled current inverting transconductance amplifier and a floating capacitor. Utilization of a fractional-order capacitor (FoC) C0,06 with 12 pF " sec.04 value for magnitude response optimization of the filter is investigated. FoC was emulated via 4th-order Valsa RC network and values optimized using modified least squares quadratic method. In frequency range MHz-I GlIz it shows only +0.5 degree phase angle deviation and the relative pseudo-capacitance error varies from-1.85% to +0.73%. SPICE simulations are given to prove the theory.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
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OECD FORD branch
20201 - Electrical and electronic engineering
Result continuities
Project
Result was created during the realization of more than one project. More information in the Projects tab.
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 2018 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)
ISBN
978-1-5386-7392-8
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
129-132
Publisher name
IEEE
Place of publication
Windsor, Canada
Event location
Windsor, Canada
Event date
Aug 5, 2018
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000458657500033