Designing constant phase elements of complement order
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F18%3APU129418" target="_blank" >RIV/00216305:26220/18:PU129418 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1007/s10470-018-1257-7" target="_blank" >http://dx.doi.org/10.1007/s10470-018-1257-7</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1007/s10470-018-1257-7" target="_blank" >10.1007/s10470-018-1257-7</a>
Alternative languages
Result language
angličtina
Original language name
Designing constant phase elements of complement order
Original language description
Once designing analogue fractional-order function blocks, the capacitive and/or inductive fractional-order elements (FOEs), also referred to as constant phase elements, being defined with their fractional order a (0<a<1) are required. Although currently capacitive FOEs are being discussed in the literature, still these passive elements are not readily available in discrete form and mainly do not offer the whole span of a. Therefore, to overcome such an obstacle, we primary propose the transformation of FOEs and their fractional order a to obtain the complement order b, whereas b = 1-a. Following the theory and mathematical description, also other transformation cases on fractional-order element are discussed and analysed in this paper. Using simple impedance converter employing single current conveyor and transconductance amplifier, the theoretical presumptions are verified both by simulations and experimental measurements.
Czech name
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Czech description
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Classification
Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
20201 - Electrical and electronic engineering
Result continuities
Project
<a href="/en/project/GA16-06175S" target="_blank" >GA16-06175S: Synthesis and Analysis of Fractional-Order Systems Using Non-Conventional Active Elements</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Name of the periodical
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
ISSN
0925-1030
e-ISSN
1573-1979
Volume of the periodical
97
Issue of the periodical within the volume
1
Country of publishing house
NL - THE KINGDOM OF THE NETHERLANDS
Number of pages
8
Pages from-to
107-114
UT code for WoS article
000445367800012
EID of the result in the Scopus database
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