CHIRP SINE GENERATION ON FIX-POINT FPGA

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F19%3APU134434" target="_blank" >RIV/00216305:26220/19:PU134434 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
CHIRP SINE GENERATION ON FIX-POINT FPGA
Original language description
This paper deals with a logarithmic and a linear chirp sine generation on a ﬁx-point FPGA. Basic overview of the logarithmic chirp sine signal and its usage is provided. Then, methods of software signal generation are described and their pros and cons are mentioned. A point-to-point method, which is able to generate both signals mentioned above, is selected for implementation. Its limitations, such as resolution limit, number wrapping and result rounding, are revealed. Moreover, a formula for maximal error caused by fix-point length, signal frequency, sampling frequency and signal parameters is presented. Therefore, the parameters for a maximal error can be calculated, so the implementation can be modified to fulfil a specific application needs. Furthermore, parameters are calculated to fulfil vibration testing criteria according to IEC:60068-2-6, then the method is implemented to a fix-point FPGA and used for a vibration testing.
Czech name
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Czech description
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Publication year
2019
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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