Capacitance Multiplier Using Small Values of Multiplication Factors for Adjustability Extension and Parasitic Resistance Cancellation Technique
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F20%3APU137132" target="_blank" >RIV/00216305:26220/20:PU137132 - isvavai.cz</a>
Result on the web
<a href="https://ieeexplore.ieee.org/document/9159558" target="_blank" >https://ieeexplore.ieee.org/document/9159558</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ACCESS.2020.3014388" target="_blank" >10.1109/ACCESS.2020.3014388</a>
Alternative languages
Result language
angličtina
Original language name
Capacitance Multiplier Using Small Values of Multiplication Factors for Adjustability Extension and Parasitic Resistance Cancellation Technique
Original language description
This paper presents a new concept of a capacitance multiplier using the topology of differential voltage buffer and current conveyor, where the capacitor is connected to the current input terminal. The presented topology overcomes the typical issue known from similar solutions, i.e. creation of an undesired lossy character of the impedance plot. The added feedback path in the structure serves for minimization of the serial parasitic resistance of the current input terminal as well as the output resistance of differential voltage buffer. The electronic driving of the current and voltage internal gains of the active elements allows the adjustment of the capacitance multiplication factor as well as readjustment of the overall capacitance structure between the lossy and lossless modes of operation. The adjustment of the multiplication factor intentionally targets low ranges of gains. Despite that the multiplication factor equals or is less than 1, the range of adjustability is very wide. Simple modifications of the proposed concept leading to the differential-mode operation and enhancement of the multiplication factor are shown and explored. They were experimentally tested in more than 2 decades, from 0.03 to 5.8 nF, and controlled by single DC voltage from 0.1 to 1.0 V. The outputs of experimental measurements meet with the PSpice simulations and confirm the design validity.
Czech name
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Czech description
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Classification
Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
20201 - Electrical and electronic engineering
Result continuities
Project
<a href="/en/project/GA19-22248S" target="_blank" >GA19-22248S: Deterministic, chaotic and stochastic phenomena in the sub-micron integrated structures</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)
Others
Publication year
2020
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Name of the periodical
IEEE Access
ISSN
2169-3536
e-ISSN
—
Volume of the periodical
8
Issue of the periodical within the volume
1
Country of publishing house
US - UNITED STATES
Number of pages
11
Pages from-to
144382-144392
UT code for WoS article
000560362300001
EID of the result in the Scopus database
2-s2.0-85090269683